The present invention relates to a method for improving dielectric deposition and trench fill in semiconductor substrates or layers utilizing high-density plasma chemical vapor deposition (HDP-CVD). More particularly, the present invention is directed toward a method and system for improving the trench fill in trenches having high aspect ratios such as shallow trench isolation (STI) structures and intermetal dielectric (IMD) structures.
Chemical vapor deposition (CVD) has been used extensively to deposit dielectric material in trenches. During deposition, dielectric material will collect on the corners of the trenches, and overhangs will form at the corners. These overhangs typically grow together faster than the trench is filled, and a void in the dielectric material filling the gap is created. Many techniques have been utilized in attempts to solve the trench fill problem.
One technique which attempts to solve this problem is deposition and simultaneous etch back of the dielectric layer. This technique may be accomplished using high density plasma chemical vapor deposition (HDP-CVD). Typically, HDP-CVD is carried out in a process chamber. Precursor gases such as silane and oxygen are flowed into the chamber along with an inert gas. A plasma is formed in a reaction zone proximate to the surface of the substrate by the application of radio frequency (RF) energy. The deposition gases disassociate and react to form a silicon dioxide layer. The relatively non-reactant inert gas is ionized and used to etch the silicon dioxide layer during deposition to keep the gaps open. The flow rates, RF power and other parameters are typically controlled to produce the desired rate of deposition and etch. In this manner, trenches in a semiconductor substrate may be successfully filled.
However, such techniques do not always produce a void free trench fill for high aspect ratio trenches. For example, one technique for high aspect ratio trenches involves depositing the silicon dioxide layer in a two-step fashion. In the first step, the silicon dioxide is deposited using a low etch to deposition ratio. In the second step, the silicon dioxide is deposited using a high etch to deposition ratio. However, this approach may not be successful because the first layer of silicon dioxide may be too thin and be etched away during the second step. Alternatively, the first layer of silicon dioxide may be too thick and may narrow or close the trenches causing the formation of voids that are not deeply buried. These voids may be opened in later chemical mechanical polishing (CMP) processing steps. Additionally, these HDP-CVD processes can cause nitride liner layer erosion because the nitride portion of STI trenches may be undesirably etched.
Therefore, there is a need for a method of HDP-CVD that can produce high quality trench fill for trenches having a high aspect ratio in semiconductor layers. Additionally, there is a need for a method of HDP-CVD that does not cause substantial erosion of layers in or around high aspect ratio trenches.